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IBIS Verification
IBIS (I/O Buffer Information Specification) models have become widely accepted among EDA
(Electronic Design Automation) vendors, semiconductor vendors and system designers as the
format for digital electronics interface data. IBIS is a fast and accurate behavioral method
of modeling I/O buffers based on V/I curves data.
Sometimes you may find IBIS models with some issues in file structure or syntax. Our
company may help you to fix these problems so that your designers will be able to use
such models during project simulation with certainty.
This service includes:
- visual inspection of the IBIS file;
- checking of availability, completeness and monotonicity of all waveforms;
- test simulation with using of a standard load as well as custom test loads (optional);
- verification of the test simulation results;
- checking, defining or modification of the package data where required;
- communicating and negotiating with the IC vendor.
IBIS modeling tools we use:
- IBIS development Studio (by Edality);
- HyperLynx Visual IBIS Editor (by Mentor Graphics).
For any information regarding IBIS, please, visit http://www.eigroup.org/ibis/ibis table/models.htm
Please see some of our projects description:
PCB Design Samples.
For particular info you can post a question or request to the e-mail:
pcb_design@edality.by
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