Beyond all doubt, many of today's high-speed digital designers are concerned with the signal integrity of their designs. Some of them still enlist the services of third-party experts in order they to advise on the routing of critical signals. And in many cases, while being carried out signal integrity analysis deals with the resulting layout and any issue has to be fixed on the fly.
At the same time for boards with more than one CPU, with interface speeds higher than 1 GHz and rise time less than 100 ps alternate approach must be introduced. Up to 80% of the signals are to be considered as high-speed demanding a specific policy for analyzing them, as traditional post-layout analysis is not enough to guarantee a complete success of the design anymore.
Transmission line behavior has become so complex that it is essential to do pre-layout simulation. So before layout begins alternative layout strategies have to be evaluated for each net or bus and special rules have to be defined by taking into account manufacturing tolerances to ensure that the resulting design can function within specifications under all possible worst-case conditions.
Edality provides signal integrity analysis services at any stage of the design helping you to fix both explicit and implicit problems and thus to eliminate layout iterations.
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