Modern more or less complex electronic designs are often built upon DDR memory for fast and efficient performance. On the other hand, time for product testing is limited because of time-to-market cycle shortening. Thus release with unstable memory may cause a costly product recall of CPU-based products.
For the sake of minimizing that risk, it is necessary to perform comprehensive memory timing analysis during the design phase of the project. But the more complex design is the more challenging the analysis becomes, as complicated designs may contain multipurpose ICs with timings diversity. Then net topologies, trace impedances and terminations play an important role in waveform integrity while trace length, via spans and crosstalk affect timing.
Hence, a combined signal integrity/timing analysis is needed to guarantee proper functioning of the DDR interface. For this to be performed not only specific timing models have to be created resting on the required parameters extraction from datasheets, but the way they were defined and how they to be interpreted should be realized.
Though JEDEC specifies timing requirements, they may vary from manufacturer to manufacturer or even from chip to chip. Therefore thorough knowledge of different timing parameters of a DDR device is mandatory for performing detailed and accurate timing analysis. And Edality is glad to give its customers the benefit of such experience.